To create advanced semiconductors such as high-bandwidth memory (HBM), integrated technology for efficiently stacking chips is essential. Existing technology has reached physical and technical limitations, and new integration strategies have emerged as important competitive factors in the industry.
In this context, a joint research team from South Korea and the United States has developed a new 3D semiconductor integration technology that can vertically stack chips. Professor Kim Ji-hwan from the Massachusetts Institute of Technology (MIT), along with international collaborators from Samsung Electronics Research Institute (SAIT) and Sungkyunkwan University, announced on the 19th that they have developed a technology that can stack new chips in a single-crystal form on semiconductor chips at low temperatures. The research results were published that day in the international academic journal Nature, and the relevant technology has already been patented.
Semiconductor integrated circuits (ICs) are continuously shrinking to improve performance and power efficiency. However, there are limitations to simply reducing the width and height, so the 3D integration concept, which saves space by stacking new circuits vertically on existing circuits, is gaining attention.
However, it has been difficult to stack single-crystal semiconductors on chips using existing 3D integration methods. Unlike polycrystalline materials, single-crystal semiconductors have consistent and superior performance but can only be grown at high temperatures above 600 degrees Celsius, which poses a significant risk of damaging underlying circuits. Additionally, the process was complex because a semiconductor layer had to be stacked on the chip first before adding the single crystal.
The research team developed a technology to stack single-crystal semiconductors directly onto chips at low temperatures below 385 degrees. Professor Kim Ji-hwan explained, "We created a finely patterned area (trench) on the chip stacked on a wafer and used a 'limited growth' method to place semiconductor single crystals in this part," adding, "By using the edges or ends of the trench as 'seeds' for the crystals to grow, we were able to stably stack single-crystal semiconductors even at low temperatures."
Based on this, the research team implemented complementary metal-oxide-semiconductor (CMOS) transistors made from metal oxide semiconductors. The resulting transistors demonstrated high performance and minimal variability without damaging existing circuits. In particular, since they were made from single crystals, power efficiency and performance remained consistently high.
The research team noted, "Because we can stack semiconductor materials directly onto chips, we can stack a large number of chips very closely together, which allows for maximizing semiconductor integration density and performance, and it will also become possible to integrate both memory and logic circuits simultaneously."
This research was carried out through close collaboration between university researchers and Samsung Electronics Research Institute. Professor Kim remarked, "This research is a rare example of corporations and universities collaborating to achieve results," expressing that the outstanding technological capabilities of Samsung Electronics researchers combined with the ideas from research teams such as MIT resulted in the development of next-generation 3D integration technology.
The research team plans to further advance the technology. Professor Kim added, "To commercialize the technology, it is essential to expand from the 2-inch diameter wafers used this time to large-scale wafer processing," expressing hope that by the 2030s, technologies for stacking semiconductors without separate wafers will be commercialized.
Reference materials
Nature (2024), DOI: https://doi.org/10.1038/s41586-024-08236-9