Samsung Electronics has confirmed its entry into trial production of the 'logic die', which serves as the brain for the sixth generation high-bandwidth memory (HBM4), through 4NANO (nanometer, 1 billionth of a meter) foundry semiconductor manufacturing processes. After completing final performance verification of the logic die, Samsung Electronics plans to deliver the developed HBM4 to its clients for testing. Having lost its lead in the HBM market to SK Hynix, Samsung Electronics is deploying advanced processes for HBM4 to launch a counteroffensive this year.
According to industry sources on the 3rd, Samsung Electronics' Memory Business Division recently completed the design of the HBM4 logic die and initiated production by handing over the design to the 4NANO foundry line. The logic die is a key component located at the bottom of the HBM, built by stacking DRAM, and it acts as the brain that controls the multilayered DRAM.
Having ceded the HBM3E (fifth-generation HBM) market to competitors such as SK Hynix, Samsung Electronics is planning to maximize the performance of HBM4 by applying advanced processes. Starting with HBM4, unlike the existing HBM3E, which only concatenated DRAMs and connected them to clients' graphic processing units (GPUs), the logic die implemented at the bottom of HBM will utilize foundry processes. Custom HBM production optimized for design assets (IP) and applications requested by clients will also be possible. SK Hynix, which does not have its own foundry capabilities, is reportedly producing logic dies using TSMC's 5NANO process.
Samsung Electronics is said to be applying a more advanced 4NANO process to improve not only the performance of HBM but also its power efficiency. An industry insider stated, 'Heat generation is difficult to control and is known as the biggest enemy of HBM,' adding, 'The logic die is where heat generation is most severe, and I understand Samsung Electronics is massively applying the 4NANO process to improve overall performance and power efficiency.'
A source familiar with Samsung Electronics' situation noted, 'It is true that we no longer have the strengths to create a significant gap with competitors in the memory business as we did before,' and added, 'As we possess foundry processes ourselves, we are optimistic about quickly manufacturing logic dies to respond to clients' bespoke needs.'
Samsung Electronics is reportedly planning to utilize 6th generation (c) 10NANO DRAM chips for the general DRAM stacked in HBM, in addition to the logic die. SK Hynix is applying 5th generation (b) 10NANO DRAM. Generally, as DRAM processes evolve, advanced processes are applied which reduce size while improving performance and power efficiency.
Samsung Electronics is said to be planning to apply a new method called hybrid bonding for the stacking of 16-layer HBM4 products. Hybrid bonding is a process that stacks chips through copper without using the 'bumps' that traditionally connected chips, allowing for size reduction while enhancing performance. Samsung Electronics has utilized the 'advanced thermal compression non-conductive adhesive film (TC-NCF) technology' which involves placing film-like materials every time a chip is stacked up to 12-layer HBM products.
An industry insider stated, 'Samsung Electronics is currently progressing rapidly in foundry processes,' and added, 'Having lagged behind competitors in previous generations, we are accelerating the schedule for HBM4 to respond swiftly to client sample testing and requests for improvements.'