Jang Tae-soo, the Vice President of SK hynix, receives a presidential citation for his contributions to enhancing the competitiveness of the domestic semiconductor industry through the development of 16Gb (gigabit) DDR5 DRAM, which applies 10nm-class 1c ultra-fine process technology, at the 52nd Industrial Day commemorative ceremony held on Nov. 19. /Courtesy of SK hynix

Vice President Jang Tae-soo of SK hynix said on the 20th, "With the development of the 6th generation (1c) DDR5 DRAM, SK hynix will further solidify its technological leadership."

Vice President Jang stated this during an interview with the SK hynix newsroom. Jang is an expert who has dedicated 20 years to memory leading technology and device research, having participated in core technology development over 10 generations, from 44 NANO (nanometers, 1 billionth of a meter) to 10 NANO.

Earlier, on the 19th, Vice President Jang received a presidential citation for his contributions to enhancing the competitiveness of the domestic semiconductor industry by developing a 16Gb (gigabit) DDR5 DRAM using 10 NANO-class 1c fine process technology at the 52nd anniversary ceremony of the Chamber of Commerce.

Since participating as the overall leader of the '1c DRAM Development Task Force (TF)', Vice President Jang achieved the world's first development of 1c DDR5 DRAM in the shortest period. The 1c process technology is considered a cutting-edge leading technology that enhances memory performance and reduces power consumption, deemed essential for the growth of high-performance computing (HPC) and artificial intelligence (AI).

Regarding the achievement of developing this technology first in the world, Vice President Jang stated, "By proactively supplying ultra-fast, low-power products to customers and quickly entering the premium market, we can gain the advantage of capturing early demand."

Vice President Jang expressed hope that the technology developed this time would also contribute to enhancing high bandwidth memory (HBM) performance. Reducing the DRAM cell size allows capacity to be increased while maintaining the chip size and height of HBM, and various designs can be attempted within HBM to add multiple functions.

Vice President Jang noted, "The smaller chips and reduced power through miniaturization have a positive effect on HBM thermal management," adding, "The completed HBM is expected to accelerate the development of the AI industry."