Jeong Myeong-su, CEO of Panesia and a chaired professor in the School of Electrical Engineering at KAIST, is selected as the January recipient of the Republic of Korea Scientist and Engineer Award./Courtesy of Ministry of Science and ICT

Jeong Myeong-su, CEO of Panesia and a chaired professor in the School of Electrical Engineering at KAIST, was selected as the January recipient of the Republic of Korea Scientist and Technologist Award.

The Ministry of Science and ICT and the National Research Foundation of Korea (NRF) select one researcher each month who has produced original research results over the past three years and greatly contributed to the advancement of science and technology, and present the Minister's Award and 10 million won in prize money. The award was previously called the Scientist and Technologist of the Month, but starting this year it has been elevated to the Republic of Korea Scientist and Technologist Award.

CEO Jeong was recognized for reducing AI infrastructure expense and improving efficiency with modular artificial intelligence (AI) data center architecture design technology.

Large-scale AI services such as the widely used ChatGPT require large amounts of computation and memory, and run on ultra-large systems that consolidate millions of devices. However, in the conventional approach, the ratios of central processing units (CPUs), graphics processing units (GPUs), AI accelerators, and memory are fixed, making it difficult to adjust them for actual use.

To solve this, CEO Jeong designed a modular AI data center architecture that allows different devices to be freely combined and used as needed, and prepared a design guide introducing consolidation methods among multiple devices, L.I.N.C and device topologies, and more.

In particular, based on Compute Express Link (CXL), a next-generation consolidation standard, the team developed a low-power, high-efficiency L.I.N.C technology that separates and manages different system devices on different nodes. It also proposed integrating accelerator-centric L.I.N.C technologies and High Bandwidth Memory (HBM) semiconductor technology into a modular AI data center architecture.

Jeong Myeong-su said, "We recently developed the world's first PCIe 6.4/CXL 3.2-based fabric switch and are distributing sample chips to partners to verify the potential for mass production," adding, "Beyond the standalone performance of each device, I hope to contribute to securing national competitiveness in AI infrastructure through continued research on L.I.N.C technologies that can efficiently consolidate and utilize them."

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