As data-centric computing and artificial intelligence (AI) technologies spread rapidly, demand is growing for high-capacity, low-power storage devices. But the widely used NAND flash memory has had the drawback of high power consumption due to inherent structural limits.
Amid this, researchers at Samsung Electronics announced a new ultra-low-power memory technology based on ferroelectric transistors (FeFET) that can increase storage capacity while using almost no power. The study was published in the international journal "Nature" on the 27th.
NAND flash has a "string" structure in which multiple memory cells are connected in a row. The problem is that to read data from any cell, voltage must also be applied to other cells before and after it. This is called "pass voltage." Because of this, there has been a structural limit in which power consumption increases as the number of memory cells increases.
On the other hand, if you try to reduce pass voltage, the signal margin that distinguishes memory cells decreases, making "multilevel storage," which stores multiple values in a single cell, more difficult.
To solve these problems, the researchers developed FeFET-based memory using a ferroelectric material. A ferroelectric material allows control of polarization direction with an external voltage and maintains that state for a long time even after the voltage is removed, and this property is used for memory. The researchers developed a new FeFET by combining hafnia ferroelectric doped with zirconium and an oxide semiconductor channel.
Memory applying the new FeFET stably stored up to 5 bits per cell even with pass voltage reduced to effectively near zero. According to the researchers, this is similar to or better than current commercialized NAND technology.
In particular, it showed up to 96% potential power savings in the string structure compared with conventional NAND. In effect, it can store much more data while using almost no electricity. It could affect applications where energy efficiency is critical, such as AI servers, mobile devices, and Edge Computing.
The researchers confirmed that performance is maintained even when the developed FeFET is fabricated in a three-dimensional (D) structure that stacks vertically like existing NAND. In particular, it operated stably even in very small cells with a short channel length of 25 nm (nanometers, one-billionth of a meter), showing no issues for high-density integration.
This study is significant in that it addresses the fundamental limit of NAND flash that "lowering power reduces capacity, and increasing capacity raises power."
In the paper, the researchers said, "The FeFET-based structure developed this time is a next-generation memory technology that can simultaneously improve capacity, power efficiency, and reliability," and noted, "As NAND-based architectures are recognized as promising platforms for neuromorphic computing and in-memory computing, it could be applied to mitigate rising energy consumption."
References
Nature (2025), DOI: https://doi.org/10.1038/s41586-025-09793-3