The College of Engineering at Seoul National University said on the 23rd that Professor Choi Jae-hyeok's lab in the Department of Electrical and Computer Engineering received the Presidential Award at the 26th Korea Semiconductor Design Contest.
The Korea Semiconductor Design Contest is a semiconductor design competition jointly organized by the Ministry of Trade, Industry and Energy and the Korea Semiconductor Industry Association, aiming to cultivate design capabilities and uncover creative ideas among university and graduate students in semiconductor design. This awards ceremony will be held on the 23rd at Coex in Samseong-dong, Seoul, and the team receiving the Presidential Award will be given 5 million won in prize money.
This year's Presidential Award recipients are students Seo Jeong-beom, Shin Yu-hwan, Lee Jun-seok, and Lee Ju-han, who are enrolled in the Department of Electrical and Computer Engineering at Seoul National University, recognized for developing a low-power clock distribution chip for next-generation High Bandwidth Memory (HBM) semiconductors.
HBM is a memory adopted to maximize the data transfer bandwidth between the graphics processing unit (GPU) and memory. To ensure the smooth operation of the thousands of data pins (DQ) inside HBM, a 2.5 GHz quadrature clock signal must be precisely distributed. However, existing methods had constraints such as quadrature phase error, high power consumption, vulnerability to noise (jitter), and limits in responding to immediate clock toggling.
To solve these problems simultaneously, the research team devised a new quadrature clock distribution and generation architecture based on injection locking. First, phase information without error is sequentially embedded in a single low-frequency clock and distributed, and then it operates on the principle of restoring this via an injection locking technique to generate an accurate quadrature clock. In this process, previously occurring quadrature phase errors can be drastically reduced, and because there is no need to directly distribute four clocks in parallel, power consumption can be significantly reduced to one-tenth or less.
Furthermore, because injection locking has strong resistance to external noise, it can maintain stable clock signal quality even in situations with power fluctuations or environmental noise. It also has a significant differentiator in that it enables immediate clock on/off control, which is required by the characteristics of the HBM interface.