When designing semiconductors, the "simulation" process—running virtual experiments on a computer before actual fabrication—is essential. In this process, researchers pre-calculate how current flows and what the heat generation and electrical characteristics are. But the more advanced the semiconductor, the more complex the structure becomes, and simulations have often taken from hours to days.
The Gwangju Institute of Science and Technology (GIST) said on the 16th that a research team led by Professor Hong Seong-min of the School of Electrical Engineering and Computer Science has developed a new algorithm that can perform such calculations up to 100 times faster than before.
A semiconductor's performance depends on how fast and accurately current flows. But building and testing it in the real world takes too much time and expense. So researchers use a tool called "TCAD simulation." Simply put, it is a kind of "virtual semiconductor experiment" that mathematically calculates the flow of electrons and the voltage distribution inside a chip.
The problem is that as semiconductor structures become more complex, these calculations are slowing exponentially. In particular, next-generation devices such as gate-all-around (GAA) and complementary FET (CFET), which have drawn attention recently, take from several hours to several days for a single simulation.
The researchers focused on eliminating the "bias ramping" process, the stage that creates the biggest computational bottleneck. Bias ramping stabilizes the computation by gradually increasing the voltage, and it accounts for most of the total calculation time.
Instead, the team used a "quasi-one-dimensional modeling" technique to simplify complex 3D structures and applied "region-wise structural analysis" to divide the semiconductor into multiple segments, applying the most suitable computational model to each segment.
Simply put, instead of computing the entire semiconductor at once, the method finely partitions it along the direction of current flow, performs a quick preliminary calculation, and then carries out a precise calculation based on those results. Thanks to this, simulations can be performed far more stably and 10 to as much as 100 times faster.
Recently, there have been attempts to shorten calculations using artificial intelligence (AI), but they had the limitation of requiring retraining even with slight structural changes. The researchers said the algorithm in this study is highly practical because it can be applied immediately to a variety of semiconductor structures without AI training.
The team validated the new algorithm on several next-generation semiconductors, including GAA and CFET. As a result, it was 10 to 100 times faster than conventional TCAD simulations while keeping the error within 0.1 volt. The consistency of results was also maintained even when device geometries or mesh conditions changed.
Hong said, "This study is significant in that it shows computing speed can be dramatically increased without AI models," adding, "It will greatly improve the efficiency of next-generation semiconductor device development going forward."
This research was supported by the Ministry of Science and ICT and the National Research Foundation of Korea (NRF) under the individual basic research program (mid-career). The results were published on the 25th of last month in the international journal "Communications Engineering."
References
Communications Engineering (2025), DOI: https://doi.org/10.1038/s44172-025-00509-z