Taiwan's TSMC, the world's largest foundry (contract semiconductor manufacturer), is expected to sharply expand its advanced process capacity, including 2-nanometer (nm, one-billionth of a meter) and 3-nanometer nodes next year, to meet rising demand for artificial intelligence (AI) chips.
According to Taiwan media including the United Daily News on the 14th, TSMC recently shared plans across the semiconductor supply chain to ramp up 2-nanometer and 3-nanometer processes next year.
TSMC's monthly 2-nanometer capacity is expected to rise about 22%, from 90,000 wafers at the end of this year to 110,000 by mid-next year. For 3-nanometer, the goal is to expand from 120,000–130,000 wafers per month at the end of last year to 180,000 at the end of this year and 210,000 by mid-next year. If the plan stays on track, 3-nanometer capacity will increase about 70% from late 2025 to mid-2027.
To boost output, TSMC is reportedly adding 3-nanometer wafer facilities in Taiwan, Arizona in the United States, and Japan, and is also pushing to convert some 5-nanometer lines to 3-nanometer. With rising investment in advanced nodes, projections are that next year's revenue will set a record high.
It is also accelerating next-generation process development. Following its A16 (1.6-nanometer) process, TSMC is said to be developing A14 (1.4-nanometer), A13 (1.3-nanometer), and A12 (1.2-nanometer) technologies. Taiwan media reported that in this process the company is working with ASML to introduce 12-inch photomasks.
TSMC declined to directly comment on the reports and said that information related to capacity should be based on materials the company has officially released.
At its second-quarter earnings briefing in Jul., TSMC said demand for advanced processes for AI remains strong and that it had secured demand visibility through 2029–2030 based on orders from major customers and cloud service providers. Accordingly, it raised this year's annual capital expenditure outlook from the $50 billion range to $60 billion–$64 billion (about 80.6 trillion–86 trillion won). It plans to allocate about 70%–80% of that to advanced processes.
It is also increasing advanced packaging capacity. To meet demand from AI Semiconductor customers such as Nvidia, TSMC plans to produce CoWoS (chip on wafer on substrate) at its Zhubei Plant 7 (AP7).