Apple's new mobile application processor (AP) A20 Pro product image./Courtesy of Apple

Apple on the 9th (local time) unveiled the new mobile application processor (AP) "A20 Pro," the first iPhone system-on-chip (SoC) to use the 2-nanometer process. The key change is faster on-device (embedded) artificial intelligence (AI) processing. The A20 Pro will power the iPhone 18 Pro, Pro Max, and Apple's first foldable phone. Qualcomm is also set to release a new 2-nanometer Snapdragon later this month, setting the stage for a head-to-head showdown over 2-nanometer mobile APs in the second half.

◇ CPU, GPU, and AI performance all improve

Apple's newly announced A20 Pro narrows the node from 3 nanometers to 2 nanometers, packing more transistors into the same area, its most notable feature. As a result, the performance of the central processing unit (CPU) core that serves as the brain is up to 20% faster than the previous generation, and the graphics processing unit (GPU), which handles graphics, increases core count to boost performance by 40%.

It is particularly notable that Apple added dedicated AI compute circuits to both the low-power cores and the GPU. Apple said it designed the chip to speed up response when the smartphone handles Generative AI features on the device without sending requests to cloud servers. The neural engine dedicated to AI computation also doubles performance over the previous generation, which is expected to make photo correction and the voice assistant—long seen as a weak point of the iPhone lineup—faster and smoother.

Apple also reworked the cooling structure to control heat. For the first time on iPhone, it brought over a packaging structure previously used only in iPad Pro and Mac M-series chips so the heat-generating semiconductor die directly contacts the vapor chamber. The surface area of the vapor chamber that dissipates heat is up to three times larger than on the iPhone 17 Pro. The redesign aims to reduce "throttling," where performance drops sharply under sustained loads such as gaming, and to maintain peak performance longer.

◇ 2-nanometer wafer and memory prices surge; Qualcomm to enter 2-nanometer late this month

Inside TSMC Fab 12 at the Hsinchu Science Park in northern Taiwan./Courtesy of TSMC

The problem is that consumers may have to shoulder higher production costs with the 2-nanometer transition. The backdrop for the pricing shift is higher foundry (contract chip manufacturing) rates. According to Taiwanese media, Taiwan's TSMC 2-nanometer (N2) wafer pricing is around $30,000 per wafer, about 62% more than 3-nanometer wafers ($18,500 per wafer). Compared with 4- and 5-nanometer wafers ($15,000 per wafer), it is about double. TSMC is reportedly planning to raise 2-nanometer wafer prices by about 10% from $30,000 to $33,000 starting in 2027.

Soaring memory prices are another factor. Market researcher TrendForce said second-quarter contract prices for commodity DRAM jumped 58% to 63% from the first quarter, while NAND flash rose 55% to 60%. In the third quarter, the pace moderated to 13% to 18% for DRAM and 10% to 15% for NAND, but double-digit gains continue. DRAMeXchange data also shows the fixed trading price for DDR4 8Gb commodity products surged 61.5% from $13 at the end of the first quarter to $21 at the end of the second quarter, and reached $25 in August. Market researcher Counterpoint Research estimates memory accounts for 40% of smartphone manufacturing costs, and the industry says higher 2-nanometer AP costs and surging memory prices will inevitably be passed on to consumers.

Meanwhile, Qualcomm is also set to announce a new Snapdragon built on the 2-nanometer process this month. With Apple moving first to 2 nanometers, the foundry process generation gap that had opened is set to narrow again with Qualcomm's new release. A semiconductor industry official said, "With 2-nanometer wafer prices more than 60% higher than 3 nanometers and DRAM and NAND prices surging at the same time, it is difficult for Apple to fully absorb the higher costs," adding, "If Qualcomm releases a new chip on the (TSMC) 2-nanometer process, the two companies will share the foundry cost burden, which could somewhat ease wafer price pressure."

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