China's largest DRAM maker, CXMT, has begun trial production of fourth-generation high-bandwidth memory (HBM3), but its initial Production yield is barely improving. It is said to be stuck at 25%, about one-third of the so-called "golden Production yield" of 80% that serves as the benchmark for mass production in the semiconductor industry. The gap is clear compared with SK hynix, which has mass-produced the same product since 2022 and secured a Production yield above 90%. The industry points to differences in the maturity of through-silicon via (TSV)—the key process that stacks and links multiple layers of DRAM—as the fundamental cause.
◇ "DRAM level has improved, but HBM stacking is a different issue"
According to a senior executive in the semiconductor equipment industry familiar with CXMT's situation on the 9th, the Production yield of CXMT's HBM3 8-high (8-Hi) product remains around 30% in the front-end process. Even among those that survive this stage, only about 70% are accepted as final good units after the back-end process. Simply put, if production starts with 100 HBM3 units, nearly 80 of them fail in the final test.
CXMT is said to be supplying a small number of HBM samples produced this way to Chinese corporations such as Alibaba T-Head and Cambricon while continuing work to improve the Production yield. The issue is not the microfabrication technology of DRAM itself. A semiconductor equipment industry official said, "There are no major issues with general DRAM made with CXMT's 'G4' (17-nanometer-class) process used for HBM," adding, "However, DRAM dies used for HBM have a larger area than general products and tighter electrical specifications, so even with the same process, it is much harder to pass the acceptance criteria."
This means that while CXMT's basic capability to make general DRAM has risen to a considerable level, a bottleneck is occurring in the step of turning it into a high-performance product called HBM. The industry says TSV lies at the core of this bottleneck.
◇ The real hurdle is TSV… "You can't catch up without years of know-how"
TSV is short for "through-silicon via," referring to the fine copper interconnects that vertically penetrate each layer to exchange electrical signals when stacking DRAM in multiple layers as in HBM. It is a high-difficulty process in which a single DRAM wafer is thinned down to a thickness of tens of micrometers—only a fraction of a hair's width—and then thousands of microscopic holes are drilled into that thin silicon plate and filled seamlessly with copper. If even one hole is misaligned or not properly filled, the entire layer can be scrapped as defective, making it one of the most precision-demanding steps in semiconductor manufacturing.
The consensus in the industry is that the technology gap between CXMT and the leading companies widens most in this process. According to analysis by semiconductor research firm Nomad Semi, Samsung Electronics' HBM2 (second-generation HBM) has more than 5,000 TSVs per die and SK hynix's HBM3 has more than 8,000, whereas CXMT is understood to have around 3,000. Having fewer TSVs means sacrificing bandwidth (data throughput) in exchange for lowering process difficulty, yet CXMT's Production yield still significantly trails Samsung Electronics and SK hynix. Even SK hynix has publicly said that its standalone TSV process Production yield was only 40%–60% in 2024, underscoring that TSV is a challenging process even for the industry leader corporations.
On top of that, Production yield loss also occurs in the back-end (stacking and bonding) stage where the dies are actually stacked and attached. If even one of the eight dies is misaligned, if microbubbles form at the junction, or if warpage occurs during the thermal compression process, the entire stack is scrapped as defective. As the number of layers increases, the number of potential failure points rises in tandem, making the difficulty grow exponentially. Given that CXMT is showing such a low Production yield even at 8-high stacking, there are projections that it could face greater challenges when moving to higher stacks such as 12-high.
A semiconductor industry official said, "The TSV process is an area that stabilizes only after years of accumulated know-how in handling wafers," adding, "Chinese companies have quickly narrowed the gap in the microfabrication technology of DRAM itself, but back-end know-how such as TSV and bonding is difficult to catch up with in a short period." The official added, "However, Samsung Electronics also had a precedent of its initial HBM4 (sixth-generation HBM) mass-production Production yield falling below 60% in Feb. and then raising it to 80% within six months, so it is premature to conclude that CXMT's 25% Production yield is a 'failure.'"