As artificial intelligence (AI) models demand more computation, power consumption rises sharply. Improving energy efficiency is the technical challenge, and I believe three-dimensional (D) scaling (a technology that vertically expands semiconductor structures to increase density and consolidation efficiency) could be the solution.
Mukund Srinivasan, group vice president at Applied Materials, said this at a press briefing titled "DRAM and advanced packaging for the AI era" held on the 31st at Oakwood Premier COEX Center in Gangnam-gu, Seoul. The event took the form of a conversation in which Srinivasan and Park Kwang-sun, head of Applied Materials Korea, explained bottlenecks in the AI Semiconductor industry and the technology roadmap.
Applied pointed to the "memory wall," a bottleneck arising from the performance gap between processors and memory, as the key obstacle to improving AI performance. Compute chips advance rapidly, but memory, which stores and supplies data, cannot keep up, limiting system performance and power efficiency.
To solve this, Applied presented a technology roadmap that upgrades the entire data movement path from DRAM devices to high bandwidth memory (HBM) and co-packaged optics (CPO). It will apply materials and process technologies used in advanced logic semiconductors to DRAM, further refine vertical stacking and bonding for HBM, and bring memory and compute chips into closer consolidation to shorten data travel distance and reduce power consumption.
Applied is a semiconductor and display equipment corporations founded in 1967 in California, United States. It supplies equipment across core semiconductor processes, from deposition, etch, ion implantation, and chemical mechanical polishing (CMP) to metrology, inspection, and advanced packaging. In the third quarter of the 2026 fiscal year (April–July), revenue was $9.12 billion (about 12.5 trillion won) and operating profit was $3.08 billion (about 4.22 trillion won), both record quarterly highs.
◇ From DRAM to HBM in "3D"… "we must move to hybrid bonding"
Srinivasan cited as key tasks for realizing 3D semiconductors: ▲ new materials ▲ precision processes that add or remove material only where needed ▲ process control at the 0.1 nm (nanometer, one-billionth of a meter) angstrom (Å) level ▲ co-optimization across processes. Logic semiconductors go through more than 2,000 steps and memory more than 1,200, so there are limits to improving each step in isolation.
Applied analyzed that, even in DRAM, advanced logic semiconductor process technologies—such as "epitaxy," which precisely grows specific materials to match crystal structures, and wiring advancement—are being applied to peripheral circuits. Looking ahead, it expects development toward making memory cells and peripheral circuits on separate wafers and then combining them, adopting the 4F² structure that stands transistors vertically to pack memory cells into a smaller area, and ultimately 3D DRAM, and it plans to support related process technologies.
In HBM, it proposed hybrid bonding—eliminating microbumps, the tiny bump-shaped electrodes that consolidate chips, and directly attaching copper pads—as the core. As the number of stacks increases, more DRAM must be built within a fixed height while also shortening data travel distance between chips.
Srinivasan said, "To keep scaling HBM energy efficiently, we need to move from microbump-based stacking to hybrid bonding," adding, "Hybrid bonding reduces the gap between dies to effectively near zero." He said it "improves thermal performance and I/O density, lowering latency and increasing bandwidth."
On the timing for mass production, he noted, "At inflection points for new semiconductor technologies, there is always a learning curve," and added, "We expect today's technical issues to be resolved." He said, "The exact commercialization schedule is for customers to decide."
◇ Turning electrical wiring into light… targeting "data movement" with CPO
Applied sees CPO, which goes beyond shortening distances between chips by changing the signal transmission method itself from electrical to optical, as a next-generation solution to AI bottlenecks. CPO integrates an electronic chip and an optical chip into a single package to transmit data as optical signals. The goal is to lower bandwidth and power-efficiency limits for AI accelerators and data centers.
Srinivasan said, "CPO is a very promising technology and will start to replace some electrical wiring inside packages," adding, "We are focusing on new materials and new process technologies to realize waveguides (light travel paths) that transmit light." He added, "We are working closely with customers aiming to implement CPO, and the hybrid bonding under development for HBM is also one of CPO's foundational technologies."
Korea is a key market that accounts for 17% of Applied's total revenue. In the third quarter of the 2026 fiscal year, revenue in Korea was $1.521 billion (about 2.08 trillion won), up 31% from a year earlier. By share of revenue, it ranks third after China (28%) and Taiwan (22%).
Applied is expanding co-development of next-generation semiconductor technologies with customers such as Samsung Electronics and SK hynix, based on its Equipment and Process Innovation and Commercialization Center (EPIC) in Silicon Valley, United States. Samsung Electronics and SK hynix are founding partners of EPIC. In Osan, Gyeonggi Province, it is building Applied Collaboration Center Korea (ACC Korea) to conduct joint technology development and mass-production verification with domestic customers.
Park said, "At EPIC, we collaborate with customers from the earliest stages of technologies and materials, and in Korea we will focus on applying these to commercial devices more quickly," adding, "Once ACC Korea is completed, we will boost the pace of innovation by consolidating EPIC with Korea's research hubs and our customers."