Taiwan's TSMC has reportedly completed development and validation of its A16, a 1.6-nanometer (nm, one-billionth of a meter) class semiconductor process, and will begin mass production in the fourth quarter of this year.
According to Taiwan media including the Liberty Times on the 20th, TSMC has completed development of the A16 process that applies its backside power delivery network (BSPDN) technology called "Super Power Rail (SPR)."
A16 is an angstrom (Å, one ten-billionth of a meter) class advanced process that TSMC is introducing after 2 nm. SPR is a technology that separates signal wiring and power wiring, which were previously placed together on the front side of the wafer, and supplies power from the backside of the wafer. Through vertical backside contacts (VB), power is delivered directly to the source and drain regions of the transistors. By separating the space occupied by power lines and signal lines, it can reduce routing bottlenecks and improve power efficiency and performance, TSMC said.
It also minimizes changes to the existing front-side gate structure, device size, and layout to maintain compatibility with existing designs. Taiwan media reported that A16 is targeting artificial intelligence (AI) and high-performance computing (HPC) semiconductors as its main markets and is scheduled to enter mass production in the fourth quarter of this year. Compared with N2P, TSMC's enhanced 2 nm process, A16 reportedly delivers 8%–10% better performance at the same power, and 15%–20% lower power consumption at the same performance.
Chip density will be 8%–10% higher. TSMC is expected to use A16 as an intermediate step to move to the next-generation 1.4 nm class process, A14. A14 is under development with a goal of mass production in 2028. TSMC is also continuing investments to expand capacity for advanced processes and packaging. On the 11th, TSMC's board approved capital expenditures totaling $29.4425 billion (about 41 trillion won) for advanced processes and packaging, among other areas.
Meanwhile, as demand for AI semiconductors grows, reports said TSMC's advanced packaging capacity for "Chip on Wafer on Substrate (CoWoS)" has become tight, leading to the transfer of some packaging volumes to Intel's Malaysia plant. In the industry, attention is on the possibility that the division of labor in the AI semiconductor supply chain will expand, with TSMC handling advanced processes while outsourcing some back-end processes to external firms.