AMD put high-bandwidth memory (HBM) front and center as a key pillar to boost the performance of next-generation artificial intelligence (AI) chips. The company said it will make it a core strategy for next-generation AI accelerators to increase not only compute power but also memory capacity and speed with every annual product release.
On the 22nd (local time), at the annual event "AMD Advancing AI 2026" held at Moscone West in San Francisco, California, AMD unveiled its new AI accelerator, Instinct MI455X. On the day, Andrew Dieckmann, corporate vice president overseeing AMD's data center GPU (graphics processing unit) business, introduced the new product roadmap and said, "Each generation includes new advances not only in compute performance but also in the memory institutional sector."
◇ Bandwidth expands 2.9 times with 12‑high HBM4 stacking
From the MI455X, the memory enhancement trend became clear. Using the latest memory, HBM4 (6th‑generation HBM), stacked 12‑high, it achieves 432 gigabytes (GB) of storage capacity and 23.3 terabytes per second (TB/s) of bandwidth per chip. Compared with its predecessor MI355X, which used HBM3E (5th‑generation HBM) stacked 8‑high for 288GB, capacity is up 1.5 times and speed is up 2.9 times.
Dieckmann said this speed boost did not simply come from raising the clock. He said, "The key was increasing the number of stacked memory layers from 8 to 12 and doubling the width of the channels connecting the memory and the chip from 1,024‑bit to 2,048‑bit." Separate from compute performance improving by up to four times over the previous generation, there was a major independent gain on the memory side.
To fully tap this memory performance, the MI455X also revamped how it links with the central processing unit (CPU), the brain of the server. Its paired CPU is AMD's 6th‑generation server processor (EPYC), and the GPU and CPU are directly connected by a dedicated pathway that shuttles at 256GB per second so the CPU can access GPU memory without latency. He said, "With this design, we reduced bottlenecks in data exchange and ensured the memory enhancements translate directly into system‑wide performance gains."
The memory expansion benefits carry over to Helios, a system that groups multiple AI chips into a single rack (server cabinet). In a Helios rack combining up to 72 MI455X units, total HBM4 capacity reaches 31 terabytes (TB) and memory bandwidth hits 1.7 petabytes per second (PB/s). In other words, the chip‑level memory enhancements scale up to the rack level.
◇ "Samsung Electronics to supply most HBM4… working together on HBM4E as well"
A senior AMD official on site said, "Samsung Electronics is expected to supply most of the HBM4 volume used in the MI455X." Samsung Electronics is preparing a 36GB‑class HBM4 product stacked 12‑high, and its data transfer speed is said to be significantly higher than that of the previous generation, HBM3E.
The official said that because AMD and Samsung Electronics have been collaborating to increase memory capacity and bandwidth together, their partnership will become even stronger at the HBM4E (7th‑generation HBM) stage, the next‑generation product. HBM4E is reportedly under development targeting 16‑high stacking, capacity in the 60GB range, and bandwidth in the tens of terabytes per second.
Meanwhile, in March this year, AMD and Samsung Electronics signed a memorandum of understanding (MOU) at Samsung Electronics' Pyeongtaek business sites to expand cooperation in next‑generation memory, including HBM4. The HBM4 product that Samsung Electronics disclosed at the time is stacked 12‑high, uses a 10‑nanometer‑class (1c) process, delivers up to 13 gigabits per second (Gbps) per pin, and reportedly provides up to 3.3 terabytes per second (TB/s) of bandwidth per stack.