Intel is preparing a new gambit for its next-generation 1.4-nanometer (14A2) process. It is reportedly reviewing a hybrid structure that supplies power to both the front and back of the chip simultaneously. In the race for next-generation processes, it has once again opted for technology with high manufacturing difficulty. The industry is paying attention to why Intel and Samsung Electronics are both choosing increasingly complex technologies as they chase TSMC.
According to the semiconductor industry on the 9th, Intel is said to be reviewing a power delivery structure for the next-generation 14A2 process that utilizes both the front and back sides.
Traditionally, it has been common to supply power from the front of the chip, and more recently, back-side power delivery (BSPDN), which moves the power lines to the back of the chip, has been regarded as next-generation technology. Intel, however, is going a step further by reviewing a plan to use both the front and back sides together.
Applying this structure can shorten the distance that power travels, easing voltage drop (IR drop) and improving performance and power efficiency. The process structure, however, becomes far more complex. Manufacturing difficulty rises and the burden of securing Production yield can also increase. While the industry says actual adoption remains to be seen since it is still under review, it sees meaning in the fact that Intel is exploring a new design approach for its next-generation process.
The industry also notes this is not Intel's first such move. With the 18A process, Intel pursued a strategy of simultaneously applying the next-generation transistor structure, GAA (gate-all-around), and back-side power delivery (PowerVia). The assessment is that it is continuing a strategy to narrow the technology gap by introducing new technologies ahead of rivals.
Samsung Electronics has taken a similar path. It was the first in the industry to apply GAA to mass production at the 3-nanometer process, and it plans to apply back-side power delivery (BSPDN) technology to the reinforced 2-nanometer process, "SF2Z," slated for mass production in 2027. All are technologies with high manufacturing difficulty but the potential to improve performance and power efficiency.
TSMC, by contrast, is continuing a strategy of ramping up relatively proven technologies step by step. It introduced GAA starting with the 2-nanometer process, later than Samsung Electronics, and plans to adopt back-side power delivery beginning with the A16 process. The industry views TSMC, which already has a strong customer base and market share, as able to prioritize stable Production yield and manufacturability, while Samsung Electronics and Intel, as challengers, need differentiation even if they must accept technical risks.
In the end, even when developing the same advanced processes, the strategies differ. TSMC, the market leader, puts more weight on the stable mass production of proven technologies, while Samsung Electronics and Intel are trying to upend the game by applying new technologies first.
A semiconductor industry official said, "In the foundry (contract chip manufacturing) market, the more of a leader a company is, the more it tends to choose proven technologies, while latecomers often introduce new technologies first to reshape the market," and added, "Although the technical risks are high, success can change how the market evaluates them, so both Samsung Electronics and Intel can be seen as throwing a gambit with their next-generation processes."