Technology related to the next-generation artificial intelligence (AI) semiconductor "Z-Angle Memory" (ZAM), being developed by U.S. Intel and SAIMEMORY, a subsidiary of Japan's SoftBank, has advanced. At a recent top-tier global semiconductor conference, the team unveiled a 3-dimensional (D) high-bandwidth DRAM structure stacked nine layers high and demonstrated a stacking technique that reduces data movement energy and transmission power. ZAM is a next-generation memory chip backed by the U.S. and Japanese governments and is seen as an effort to crack the high-bandwidth memory (HBM) market dominated by Korea.
The industry is paying as much attention to who presented the work as to the technical progress itself. That is because Taiwan's Powerchip Semiconductor Manufacturing (PSMC) and AP Memory, which did not appear at the forefront when Intel and SAIMEMORY announced their collaboration in Feb., also joined the research team. PSMC is a Taiwanese foundry (contract semiconductor manufacturing) with memory process experience, and AP Memory is a Taiwanese fabless (semiconductor design) company that designs low-power memory and intellectual property (IP). Observers say a united front has formed, adding Taiwan's manufacturing and design ecosystem to U.S. fundamental technology and Japanese capital and government support to counter Korea's dominance in memory semiconductors.
◇ U.S.-Japan ZAM technology brings in Taiwan's manufacturing and design ecosystem
According to the semiconductor industry on the 26th, researchers from SAIMEMORY, Intel, PSMC and AP Memory presented a nine-layer 3D high-bandwidth DRAM structure at the 2026 IEEE/JSAP VLSI Technology & Circuits symposium. VLSI is regarded, along with the International Electron Devices Meeting (IEDM) and the International Solid-State Circuits Conference (ISSCC), as one of the world's top three semiconductor conferences. The announcement was included in the official technical Highlight of the symposium held in Honolulu, Hawaii, on the 18th.
The topic was "Multiple-wafer (9-layer), extreme thin (3µm-Si per stack) and innovative fusion-bonded via-in-one architecture for high bandwidth 3D memory."
Fusion bonding is a process that brings multiple wafers together at near-atomic contact without adhesives, and through-silicon via (TSV) refers to vertical channels drilled through a chip to electrically link circuits above and below. The via-in-one structure creates a single integrated connection path through the stacked layers so that it directly ties into each layer's metal interconnects.
The word ZAM does not appear directly in the abstract and other materials. But the techniques the researchers devised are closely related to ZAM. If HBM stacks DRAM and links layers with vertical TSVs, this paper focuses on lowering data movement power and connection resistance by combining ultra-thin silicon and via-in-one TSVs in a nine-layer structure stacking eight DRAM layers atop one logic layer.
The industry sees this as a proof-of-concept aligned with ZAM commercialization. Steven Morein, a SAIMEMORY researcher who released the technology, presented a preliminary development paper titled "Challenges and Innovations in High-Bandwidth DRAM: The Case for Z Angle Memory" at the International Memory Workshop (IMW) in May. The paper explained that ZAM combines a vertical slice structure, via-in-one bonding, and inductive-coupled I/O to address HBM's issues with power, heat, Production yield, and system integration.
Market research firm TrendForce said of the ZAM partnership that "PSMC has taken a key role in prototype production and manufacturing," and that "the U.S.-Japan-Taiwan push for next-generation AI memory could lay out an alternative memory roadmap beyond HBM and help reduce reliance on existing supply chains."
◇ HBM is an "elevator," ZAM is an "escalator"… upending the game by changing how heat escapes
ZAM is drawing attention because it targets the HBM market led by Samsung Electronics and SK hynix. According to Counterpoint Research, by revenue in the first quarter this year, global HBM market share was SK hynix 58%, Samsung Electronics 21% and Micron 21%. HBM is a key memory that supplies large volumes of data to AI accelerators from Nvidia and AMD, and as a high value-added product where supply lags demand, it has become a source of massive revenue.
HBM stacks DRAM dies and bores vertical channels with TSVs to consolidate each layer. It can be likened to installing an elevator in the middle of a high-rise so people can go up and down floors quickly. Data travels a short distance, so speed is high, but as the number of layers grows, heat is more likely to be trapped in the center.
ZAM seeks to solve this by changing the structure itself. If HBM is a vertical elevator, ZAM is closer to placing escalators that connect floors diagonally in multiple directions. Data and heat do not bottleneck in a single vertical channel; they can move along vertically oriented memory slices and exit. SAIMEMORY says ZAM forms continuous thermal conduction paths in each slice and reduces the need to drill TSVs inside individual DRAM layers, alleviating HBM's heat and Production yield issues.
Industry observers say the SAIMEMORY team showed a core stacking technology for implementing ZAM at VLSI. The researchers realized a nine-layer structure stacking eight DRAM layers on one logic layer. They thinned each DRAM layer's silicon substrate to about 3 µm and placed roughly 13,700 via-in-one TSVs per layer. The key is to directly connect each metal interconnect layer to the TSV bus to enhance the stability of signal and power delivery.
The team said this structure can reduce data movement energy to below 0.7 pJ/bit. They also said it can achieve a bandwidth density of about 0.25 Tb/s/㎟. Data transmission power was presented as under 0.35 W/㎟. The team said they also succeeded in functional verification and reliability testing of the nine-layer DRAM within a 0.95–1.2 V range.
These figures show that ZAM is not just a design concept but can operate as an actual stacked structure. It means more data can move within the same chip area while reducing the power required and the heat generated in the process. However, customer qualification and mass-production Production yield have not yet been confirmed.
◇ U.S. fundamental technology meets Japanese subsidies… commercialization targeted for 2029
ZAM is being developed with active support from the U.S. and Japanese governments. When Intel and SAIMEMORY announced their ZAM development partnership in Feb., they said they would leverage research results from the Advanced Memory Technology (AMT) program administered by the U.S. Department of Energy (DOE) and the National Nuclear Security Administration (NNSA). Sandia, Lawrence Livermore and Los Alamos national laboratories participated in the AMT program, and Intel verified next-generation DRAM bonding (NGDB) technology through it. NGDB is a technology base aimed at reducing the power and capacity limits of conventional DRAM stacking, and SAIMEMORY plans to commercialize ZAM based on it.
The Japanese government has also adopted ZAM as a next-generation semiconductor manufacturing subsidy project. In Apr., the New Energy and Industrial Technology Development Organization (NEDO) under the Ministry of Economy, Trade and Industry selected the "high-density, wide-bandwidth, low-power ZAM development" project led by SAIMEMORY and Intel's Japan subsidiary for its post-5G information and communications systems infrastructure research and development program.
The Japanese government said that as generative AI models grow, memory bandwidth is becoming a bottleneck over GPU compute performance, and current HBM has structural issues such as heat stagnation. Some Japanese media reported that NEDO's support could be up to 3.8 billion yen. Alongside this, SAIMEMORY has carried out a series A fundraising targeting Fujitsu, the Development Bank of Japan, RIKEN and SoftBank.
◇ Korea also in a vertical stacking speed race… "Taiwan's entry expands the mass-production ecosystem"
Of course, it will be difficult for ZAM to immediately replace HBM, which has emerged as the core AI memory in the market. That is because many challenges beyond technology development remain, including customer qualification, mass-production Production yield, international standards, AI accelerator package integration and large-scale supply capability. The disclosed nine-layer 3D high-bandwidth DRAM structure is also about 9 GB based on eight DRAM layers. Considering HBM4 has achieved tens of GB per stack, the gap is still large.
SAIMEMORY and Intel also aim to produce prototypes by Mar. 2028 and to commercialize in 2029. Rather than directly replacing the current fifth-generation HBM (HBM3E) or next-generation HBM (HBM4), it is more realistic to view ZAM as a competitor in the post-HBM market after 2029.
Korean memory semiconductor corporations are also accelerating vertical stacking development to counter this pursuit. Samsung Electronics announced a 16-layer vertical-stacked DRAM (VS-DRAM) at VLSI 2026. Even in DRAM, the strategy is to overcome density limits not by simple scaling but by "building upward."
SK hynix also announced a next-generation DRAM structure. At VLSI 2026, SK hynix disclosed the electrical characteristics of 4F² vertical gate (VG) DRAM. 4F² refers to a structure that theoretically minimizes the area occupied by a single DRAM cell. As it has become harder to further shrink cell area in planar structures, the approach is to stand the cell transistor's gate vertically to increase density.
If ZAM aims at an alternative memory supply chain to HBM, Samsung Electronics and SK hynix are effectively accelerating vertical stacking competition on both DRAM cells and logic devices to maintain their existing memory leadership.
A semiconductor department professor who requested anonymity said, "The entry of Taiwanese corporations, which lead the global semiconductor production ecosystem, is more than mere technical collaboration; it means the integration of process, packaging and validation know-how needed for real commercialization," and added, "Since mass-production technology is shaped by the financial resources and ecosystems that can validate repeatedly across varied environments, we should be wary of the possibility that alternative technologies backed by rival countries will narrow the gap faster than expected."