TSMC, the world's largest foundry (contract chip manufacturing) corporation, disclosed validation results for commercializing glass semiconductor substrates developed within its Taiwan- and Japan-centered ecosystem. As a result, a sense of crisis is growing among Samsung Electro-Mechanics, SKC, and LG Innotek, which have focused on glass substrates as a next-generation growth pillar and pushed for commercialization.
Glass substrates are regarded as a next-generation packaging material that can solve the warpage, heat generation, and power delivery limits of existing plastic organic substrates. As AI semiconductors grow larger, the material is expected to address problems arising at the substrate level, leading the industry to call it a "game changer." If TSMC, which holds sway over the semiconductor packaging market, builds the glass substrate ecosystem first, there are concerns that Korea's corporations could fall behind in the race for global standards and major customer certifications even with the technology in hand.
According to Taiwan IT outlet Digitimes and industry sources on the 18th, TSMC recently conveyed a plan to its supply chain for "developing glass substrates for chip-on-wafer-on-substrate (CoWoS)." The notice is said to state that Ibiden, a Japanese semiconductor packaging substrate manufacturer, and Innolux, a Taiwanese panel maker, are jointly validating the application of glass substrates to next-generation CoWoS packaging. The industry views the document as performance sharing with an eye toward future certifications by key customers and mass production validation.
CoWoS is a packaging technology that connects multiple chips such as graphics processing units (GPUs) and high bandwidth memory (HBM) at high speed on a single substrate. As demand for Nvidia AI chips has grown, CoWoS production capacity itself has become insufficient, and TSMC has pushed both CoWoS capacity expansion and next-generation packaging development in parallel.
◇ TSMC says "package substrate warpage improved 16%"… validates large AI GPU package
In this material, TSMC disclosed for the first time validation metrics for glass substrates for CoWoS. TSMC said that joint simulation validation with Ibiden and Innolux showed the package co-planarity (COP—an index of how flat the surface of a semiconductor package or substrate remains) of glass substrates improved 16% over existing levels. The effective coefficient of thermal expansion (CTE) was reduced by 19%, while the effective modulus of elasticity increased by 31%. For power integrity, resistance fell 27% and inductance (an electrical property that causes voltage fluctuations in response to current changes) dropped 42%.
These figures indicate that using glass substrates allows large AI chip packages to warp less during thermal cycles and reduces physical stress between silicon chips and the substrate. Improvements in COP and CTE reduce alignment errors and bonding defects in fine interconnects that consolidate multiple chips such as GPUs and HBMs on the substrate. A higher effective modulus with lower resistance and inductance means large chips and stacked memory can be supported more stably while cutting power loss and voltage ripples.
The industry is also watching TSMC's test conditions. TSMC conducted performance validation on a glass-core substrate 0.8 mm thick. The validation sample applied a 5x reticle CoW packaging specification and a package size of 85×110 mm. That corresponds to a large AI GPU package.
TSMC said that no microcracks or delamination—typical defects of glass substrates—appeared during testing. While glass boasts high stiffness and excellent flatness, its brittleness makes it prone to breakage; the absence of cracking and delamination in a large package is interpreted as a signal that raises the prospects for commercialization.
However, it is hard to conclude that mass production of glass substrates is imminent. TSMC told its supply chain that further research and validation are needed on glass thickness and the layout for placing multiple chips inside a large CoWoS package and consolidating them with fine interconnects.
The industry also assesses that TSMC has not yet fully solved through-glass via (TGV), cited as a core hurdle to mass production. Because glass substrates are insulating and do not conduct electricity, a TGV process is required to drill tens of thousands of microholes and fill them with copper to create vertical passages for signals and current, consolidating circuit layers on the top and bottom of the substrate.
◇ An early market targeted by Intel, Samsung, and SK… TSMC upends the board with a "surprise result"
Leaders in glass substrates have been seen as: ▲ Intel, which has focused on the technology for over 10 years ▲ Samsung Electro-Mechanics, which is producing prototype glass package substrates on a pilot line at its Sejong business sites ▲ SKC, which, through its subsidiary Absolics, has built a production base in Covington, Georgia, in the United States. LG Innotek is also operating a pilot line at its Gumi business sites, targeting commercialization in 2027–2028.
By contrast, TSMC's glass substrate development had been relatively under the radar. A semiconductor industry source said, "TSMC's latest glass substrate development results were close to a 'surprise announcement,' as there had been little concrete news," adding, "Judging solely by the disclosed figures, the level is close to commercialization, which will come as a shock to Korea's corporations."
In Taiwan, the ecosystems for outsourced semiconductor assembly and test (OSAT), substrates, and server manufacturing are tightly connected around TSMC. When TSMC sets a direction for next-generation packaging, Taiwan's back-end, substrate, and server manufacturing corporations move in concert.
An executive at a domestic semiconductor packaging company said, "The fact that TSMC joined hands with Ibiden and Innolux to disclose glass substrate validation results can be read as a move to cement the next-generation AI packaging standard first within a Taiwan- and Japan-centered supply chain," adding, "If TSMC proceeds with glass substrate validation within a supply chain connected to global AI chip customers such as Nvidia, AMD, and Broadcom, Korea's corporations may find market entry itself difficult."
Digitimes cited customer demands for technical specifications and production capacity, along with the pursuit by Intel and Samsung Electronics, as reasons TSMC is rushing to adopt glass substrates. The outlet said, "TSMC's disclosure of glass substrate results responds to growing customer requirements for technical specifications and production capacity, and to the accelerating competition from Intel and Samsung Electronics."
◇ As AI chips get larger, substrates become the bottleneck… glass substrates expected to enter initial production in 2028
As AI semiconductor architectures evolve, market interest in glass substrates is rising. As AI shifts from training to inference and then to agentic AI, real-time data throughput and token usage are surging. In the past, the performance of individual chips such as GPUs or HBM was key; now, performance depends on how quickly and reliably GPUs, CPUs, HBMs, network chips, and memory are connected. As data throughput and power delivery cross critical thresholds, larger-area and taller substrates have become essential, and substrates have been elevated from simple parts to partners that solve semiconductor bottlenecks.
Package substrate sizes are also growing in line with AI performance gains. From about 90×90 mm in 2020, they grew to 120×120 mm in 2023–2025, and projections suggest 120×150 mm will be used for AI semiconductor packaging in 2028. Some believe that after 2030, around 230×230 mm will have to be used broadly to meet AI demand. In fact, Nvidia's AI chip Blackwell GB200 used a substrate measuring 81.5×74.8 mm, while the AI chip Vera Rubin VR200, now nearing mass production, uses 100×91 mm.
As sizes increase, organic substrates exhibit various issues such as warpage due to high heat, unstable power delivery, signal loss, and stacking limits. Glass, by contrast, has low thermal expansion, a flat surface, and high stiffness, making it advantageous for large packages.
The international semiconductor industry association SEMI and market researcher GlobalNet said in a joint report on the 27th of last month that glass substrates for semiconductors will likely enter initial production around 2028 for certain high-performance applications. They projected a compound annual growth rate of 67.2% from 2028 to 2040.