Samsung Electronics has implemented three-dimensional (3D) stacked transistor technology to overcome the miniaturization limits of logic semiconductors. By applying the concept of vertical stacking used in memory semiconductors to logic semiconductors, it presented a structure that can pack more transistors into the same area.
Samsung Electronics said on the 17th that the Logic TD team at its Semiconductor Research Center implemented, for the first time in the world, a "3D stacked field-effect transistor" (3D Stacked FET) with a gate pitch of 42 nanometers (nm) at the "VLSI Symposium" 2026. The paper received the highest evaluation among more than 1,000 submissions and was selected as Best Paper.
The VLSI Symposium is considered one of the world's three major semiconductor conferences, along with the International Electron Devices Meeting (IEDM) and the International Solid-State Circuits Conference (ISSCC). Gate pitch is the distance between the centers of adjacent gates; the smaller it is, the more transistors can be placed in the same area.
The core of this research is stacking transistors vertically that were previously placed side by side on a two-dimensional (2D) plane. Logic semiconductors handle computation and control, like central processing units (CPU) and graphics processing units (GPU). As demand grows for AI and high-performance computing (HPC), logic semiconductors require technology that performs more computation in a smaller area with lower power.
Until now, the semiconductor industry has improved performance by narrowing the spacing between transistors. However, as the spacing between devices shrinks, the insulator that electrically isolates them also becomes thinner, which can cause malfunctions below a certain threshold. In other words, there is a physical limit to horizontal scaling.
Samsung Electronics applied a structure that stacks transistors vertically to solve this. In a vertical stacking structure, the thickness of the insulator separating the upper and lower devices is defined in the vertical direction, reducing constraints on horizontal area. The company said that, theoretically, twice as many transistors can be placed in the same area.
Jeong Young-chae, TL of the Logic TD team at the Samsung Electronics Semiconductor Research Center, said in an interview with the Samsung Electronics Semiconductor Newsroom, "The key is that we overcame the limit of reducing device size in the horizontal direction with a vertical stacking structure," adding, "It is an innovative structure that, by simple calculation, can pack twice as many transistors into the same area."
The vertical stacking structure was first applied to V-NAND in NAND flash and to high bandwidth memory (HBM) based on DRAM. Samsung Electronics expanded this structure into the logic semiconductor domain. Kwon Uk-hyun, a master at the Logic TD team of the Samsung Electronics Semiconductor Research Center, said, "In flash, V-NAND is the representative case, and in DRAM, it is HBM," adding, "This development trend naturally extended into logic development." In this study, the method of linking the upper and lower transistors also changed. Samsung Electronics applied "RBC" (RX Bounded Contact), which directly penetrates vertically to connect the upper and lower transistors. The conventional method used the transistor's side to make an indirect connection, but RBC directly links the transistors above and below, helping reduce device area.
However, the vertical stacking structure is highly challenging to manufacture. As structures become deeper and narrower, etching and deposition processes become more difficult, and precise process control is also required to fill insulators or metals without voids. The research team said it secured the optimal process after verifying new materials and process conditions multiple times during RBC implementation.
Samsung Electronics expects this technology to be used in next-generation logic semiconductors for AI and high-performance computing (HPC). If the number of transistors that can be placed in the same area increases, more computation can be handled with a smaller chip area, and power efficiency improvements can also be expected. The research team said that if the vertical stacking structure is applied, the number of transistors per unit area can theoretically be doubled, potentially yielding greater gains in power efficiency and performance than previous generational shifts.
The paper was also recognized for implementing an industry-minimum gate pitch of 42 nanometers and for applying three-tier nanosheet channels to both the upper and lower devices. A nanosheet channel is an ultrathin film through which current flows. The research team went beyond the existing two-tier structure to implement three-tier channels for the upper and lower transistors, and by applying a vertical through-connection method, it demonstrated the potential for improved density.
Samsung Electronics plans to carry this research forward into follow-up development that implements actual circuits. The research team sees this achievement as the stage of vertically stacking n-type and p-type transistors, the basic units that make up logic products. Going forward, the team plans to verify productization potential by developing a test circuit called a "ring oscillator," which checks whether a circuit operates normally, and "SRAM," a high-speed temporary memory circuit.
Samsung Electronics believes that implementing 3D stacked transistors with a 42-nanometer gate pitch will serve as a turning point that extends the density limits of logic semiconductors into vertical space.