As Samsung Electronics and TSMC compete in the 2-nanometer (nm) process, a domestic research team has developed a technology that predicts, at the atomic level, the physical limits of transistor miniaturization using only computer simulations.
The Korea Advanced Institute of Science and Technology (KAIST) said on the 14th that a research team led by Professor Kim Yong-hoon of the School of Electrical Engineering built a first-principles calculation-based technology computer-aided design (TCAD) platform.
The semiconductor industry has continuously downsized transistors to improve performance, but when they are reduced below a certain size, electrons escape due to the "quantum tunneling" phenomenon, making it impossible to control current. With current technology, it is virtually impossible to verify this limit experimentally.
The research team approached the problem by combining a first-principles method, which calculates the motion of atoms and electrons using only fundamental physical laws, with a self-developed theoretical framework (multispace density functional theory).
When applied to a device made of monolayer molybdenum disulfide (MoS2), a candidate material for next-generation semiconductors, the team confirmed that the "critical tunneling length," which determines the limit of transistor miniaturization, is a design variable that changes with the metal work function and contact structure. This means there is further room for miniaturization depending on the choice of material combinations and structures.
In the optimal combination among the candidate metals the team examined, they identified the potential to reduce the critical tunneling length to below 4 nm. They also proposed a design direction for next-generation devices that lowers power consumption by combining two-dimensional semiconductors with different properties.