Samsung Electronics said on the 12th that it began mass production and shipment of the world's first sixth-generation high bandwidth memory (HBM4).
Samsung Electronics set a goal from the outset of HBM4 development to exceed the standards of the JEDEC (Joint Electron Device Engineering Council), an international semiconductor standards organization. The product adopts state-of-the-art 1c DRAM (10-nanometer class sixth generation), securing stable Production yield and industry-leading performance from the start of mass production without redesign.
Hwang Sang-jun, head of memory development at Samsung Electronics (vice president), said, "Samsung Electronics HBM4 broke with precedent by applying already proven processes, and instead adopted cutting-edge processes such as 1c DRAM and 4-nanometer foundry (contract semiconductor manufacturing)," and added, "By securing ample headroom for performance scaling through process competitiveness and design improvements, we were able to meet customers' performance upgrade needs in a timely manner."
To strengthen HBM4 technological competitiveness, Samsung Electronics applied 1c DRAM and, taking into account the characteristics of the base die, adopted a 4-nanometer process advantageous for performance and power efficiency. The base die is the foundational chip at the bottom of the HBM stack that controls power and signals.
Samsung Electronics said its HBM4 has stably secured an operating speed of 11.7 Gbps, about 46% above the JEDEC industry standard of 8 Gbps (gigabits per second). That is about 1.22 times faster than the previous generation's (HBM3E) maximum pin speed of 9.6 Gbps. The company said, "It can scale up to 13 Gbps, which is expected to effectively alleviate the data bottleneck that intensifies as AI models grow larger," and added, "Samsung Electronics' HBM4 boosts total memory bandwidth per single stack to a maximum of 3.3 TB/s, about 2.7 times higher than HBM3E, exceeding the customer requirement of 3.0 TB/s."
Samsung Electronics' HBM4 offers capacities of 24 GB to 36 GB through 12-layer stacking technology. In line with customers' product schedules, the company plans to expand capacity to up to 48 GB by applying 16-layer stacking technology.
As the number of data input/output (I/O—gateways for sending and receiving data between memory and the graphics processing unit) pins expands from 1,024 to 2,048, Samsung Electronics applied low-power design technology to the core die to address the resulting power consumption and heat concentration issues. The core die refers to the vertically stacked DRAM dies that form the core of HBM. HBM consists of core dies made of DRAM and a base die that serves as the controller.
Samsung Electronics also improved energy efficiency by about 40% over the previous generation by applying a low-voltage design for transmitting and receiving silicon via (TSV) data and optimizing the power distribution network (PDN). Thermal resistance characteristics improved by about 10%, and heat dissipation characteristics improved by about 30%.
The company said, "We developed a circuit that reduces the voltage of the driving circuitry for data input and output from 1.1 V to 0.75 V, cutting TSV driving power by about 50%," adding, "Optimized for data center environments, it combines top-tier performance with stable reliability, and customers can use Samsung Electronics' HBM4 to maximize graphics processing unit (GPU) computing performance while reducing power consumption and cooling expense at the server and data center level."
Samsung Electronics operates across various semiconductor sectors, including ▲ logic ▲ memory ▲ foundry ▲ packaging. In line with HBM advancement, the company has effectively secured in-house capabilities to enhance "base die" performance.
The company said, "Through close DTCO (Design Technology Co-Optimization) collaboration between our in-house foundry processes and HBM design, we plan to continuously develop top-tier HBM that secures both quality and Production yield," adding, "We are consistently receiving requests for HBM supply partnerships from hyperscaler customers that design and develop major global GPUs and custom next-generation application-specific integrated circuit (ASIC)-based chips, and we will further expand technical collaboration with them."
Samsung Electronics expects this year's HBM sales to more than triple from last year and is preemptively expanding HBM4 production capacity. The Pyeongtaek campus phase-2 line 5, slated to go into full operation starting in 2028, will serve as a key hub for HBM production. The company also plans to continue securing stable supply response capabilities amid a medium- to long-term demand upcycle centered on AI and data centers.
Following HBM4, Samsung Electronics is also preparing HBM4E, with sample shipments planned for the second half of 2026. HBM4E is next-generation high bandwidth memory based on the fundamental structure of HBM4 that further boosts operating speed, bandwidth, and power efficiency. The company also plans to begin sequential sampling of custom HBM for customers starting in 2027.