Samsung Electronics has begun its return to "Samsung of technology," marked by the shipment of sixth-generation high-bandwidth memory (HBM4). It formalized a shift from a mere memory supplier to a corporations centered on AI system architecture that integrates and optimizes foundry, advanced packaging, and design.
Song Jai-hyuk, chief technology officer (CTO) of the Device Solutions (DS) institutional sector at Samsung Electronics, met with reporters on the 11th before a keynote at Semicon Korea 2026 at COEX in Samseong-dong, Seoul, and said, "Customer feedback on HBM4 is very satisfying," adding, "Please see this shipment as proof of Samsung's original form, responding with world-class technology."
Samsung Electronics plans to officially ship sixth-generation high-bandwidth memory (HBM4) this month for Nvidia's next-generation AI accelerator "Vera Rubin." Samsung's HBM4 achieves an industry-leading operating speed of 11.7 gigabits (Gb) per second, exceeding Nvidia's requirement of 11 Gbps. Song, the CTO, added, "Beyond HBM4, we are continuously preparing next-generation products such as HBM4E and HBM5," and noted, "What we do now is important."
In a keynote that day themed "Beyond zettaflops (10 sextillion operations per second)," Song argued for a fundamental shift in AI compute architecture. As AI technology evolves from training-centric to inference and agent AI, data center workloads are growing exponentially, and the diagnosis is that improving single-chip performance alone has hit a ceiling.
He explained that bottlenecks are shifting from compute performance to memory, interconnects, power consumption, and packaging structures, and proposed a "co-optimization" strategy—an approach at the system-architecture level beyond individual chips—as the solution.
As a concrete technical result, the hybrid copper bonding (HCB) technology now in preparation has demonstrated actual operation in a 16-high stack environment, securing meaningful figures that reduce via resistance by more than 20% and lower temperature rise by more than 12%. In addition, by proactively introducing interface IP that radically reduces the number of input/output (IO) channels, experiments confirmed the potential to cut power consumption by more than half.
In particular, the "Samsung custom HBM" architecture, being developed in close collaboration with customers, integrates compute cores into the baseline and aims to boost performance by up to 2.8 times at the same power.
In addition, Samsung Electronics is pursuing networking innovation between chiplets through a next-generation "Hi" strategy—an optical communication interface technology that mounts an optical engine within a chiplet—and plans to defend market leadership by continually securing advanced technologies beyond HBM4, including HBM4E and HBM5.
On the memory market's supply-demand outlook, Song said it is "a market with a different character than PCs or mobile," and predicted, "Demand is likely to be strong this year and next." Song, the CTO, said, "We will strengthen collaboration with materials, components, and equipment companies to secure the functions required in the AI era," adding, "We will contribute to the industry's overall evolution through Samsung's technological synergy."