With Samsung Electronics and SK hynix declaring mass production of sixth-generation high bandwidth memory (HBM4), they have reportedly postponed introducing the hybrid bonder that had been expected to be used in part for HBM4 manufacturing. Samsung Electronics and SK hynix plan to mass-produce HBM4 using TC bonders supplied by existing vendors such as SEMES and HANMI Semiconductor. Even the 16‑high HBM4 product, for which hybrid bonder adoption had initially been expected, appears likely to be implemented with a TC bonder.
According to the industry on the 3rd, Samsung Electronics and SK hynix plan to maintain the existing method of stacking DRAM with microbumps (fine-pitch bumps) by adjusting HBM4's stack height and other parameters. Bumps are conductive protrusions such as solder. By minimizing bump pitch as much as possible, they aim to extend microbump-based stacking technology by one more generation. However, Samsung Electronics plans partial use of hybrid bonders at the HBM4E stage (seventh-generation HBM), the successor to HBM4.
Hybrid bonders are undergoing research and development and testing, but more time is reportedly needed before they can be used for high-volume mass production. Hybrid bonders are being called a "game changer" for the next-generation HBM market. The TC bonders currently used in HBM manufacturing stack chips by applying heat and pressure to bumps. In contrast, hybrid bonders can attach chips without separate bumps, making them regarded as essential equipment for producing ultra-high stacks of 20-high or more. Because there are no bumps between chips, electrical signal loss can be minimized, improving semiconductor performance.
Within the industry, the need to introduce hybrid bonders has been raised to meet higher performance targets for next-generation HBM. For HBM4, the number of channels has been doubled from the prior generation to widen the interface width, and the signal speed per pin (signal line) has also been further increased. To that end, hybrid bonders capable of bonding stacked HBM without bumps have drawn attention.
However, because hybrid bonders have yet to secure mass producibility and Production yield, Samsung Electronics and SK hynix have opted for now to push TC bonder performance to the maximum. Regarding pitch scaling (reducing bump and pad spacing), the companies are said to have designed HBM4 to bring the microbump pitch down to around 10 micrometers (µm). They say this design alone can reach HBM4's target performance. Earlier, Nvidia asked the two companies to achieve about 11.7 Gb/s per pin for HBM4.
Market research firm CTT Research said, "In Aug. last year, a North American client (Micron) planned to adopt a 'fluxless bonder' that eliminates flux, but postponed it to 2028," adding, "The existing TC bonder can meet the specifications required by the JEDEC (Joint Electron Device Engineering Council), while fluxless bonders and hybrid bonders cost more than twice as much and their Production yield is under 50%."
At last month's earnings conference call for last year's fourth quarter, Samsung Electronics said, "We sent customers a sample applying hybrid bonding technology to HBM4, and we expect partial commercialization starting with HBM4E." However, word inside and outside Samsung is that TC bonders will still be used heavily even for the mainline HBM4E. A source familiar with Samsung said, "There is room to use hybrid bonders for some high-spec product lines where they are needed, but they are not yet as stable as TC bonders for high-volume mass production," adding, "There are still areas to improve in terms of price and Production yield."